This invention relates generally to the packaging of semiconductor devices. More particularly, this invention relates to a large semiconductor device package that minimizes the impact of different coefficients of thermal expansion associated with the environment in which the package exists. The invention also relates to processing techniques employed for under-filling of chip dies to thin substrates which require rigid stiffeners to control the flatness of the device packages and reduce bowing affects due to internal stresses caused, for example, by differences in coefficients of thermal expansion between material layers.
Integrated circuit geometry is becoming smaller, resulting in higher performance and functionality per unit area. While the chip circuitry is becoming more dense, the chip area is becoming larger and larger. Many of today""s chips have hundreds, and even thousands of pads, that must be electrically connected to interface with a printed circuit board (PCB) containing other electrical elements and chips. It is important that the chip connections be designed in such a way as to allow for the chip pads to interconnect with the package.
As chips contain more functions that require a connection to the package, the bond pad area at the chip perimeter is beginning to exceed the capability of current technology to make connections from the chip to the package using traditional wire bond techniques. Wire connections from these pads to the package are limited by pad pitch and size. To overcome such limitations, the makers of integrated circuits are employing techniques to redistribute the pads to locations within the outer perimeters of chips, and converting the connection techniques from wire bonding to soldering the pads directly to the package. This technique is referred to as xe2x80x9cflip chipxe2x80x9d technology. While this technology has been in existence for many years, what is now unique to this technology is the shear magnitude of the die size and the number of interconnects. It is now possible to produce die sizes in excess of 35 mm square with thousands of interconnects.
The placement of semiconductor devices onto a substrate, or a printed circuit board, is generally referred to as the die placement, die attach or die bonding operation. Die placement techniques vary depending on the assembly process used. Variations in the technique can be due to a variety of design considerations, such as the particular application of the semiconductor package or the method necessary to interconnect the die within the package.
A common method of interconnecting the die within the package is wire bonding. In wire bonding, a wire is bonded both to the die circuitry and bonded to the substrate. In another method, the xe2x80x9cflip chipxe2x80x9d approach, a semiconductor die, referred to as a xe2x80x9cbumpedxe2x80x9d die, includes patterns of contact bumps formed on a face of the die. The bumps are solder balls on the underside of the chip that are registered or aligned with solder pads on the substrate.
The bumps allow the die to be mounted to a substrate and act as mechanical and electrical contact points with integrated circuit (ICs) formed on the die. The bumped device is mounted to the substrate active side down. Since the active circuitry is facing down instead of up, as in the case for wire bonded devices, this approach is known as xe2x80x9cflip chipxe2x80x9d. This mounting process was originally developed by IBM and is also known as the C4 joining process (Controlled Collapse Chip Connection). In other structures, a silicon chip is embedded in the packaging where a top layer of bumps is not required.
Considering that the chip is in intimate contact with the package surface material, it is important that the chip surface and the package mounting surface have similar mechanical properties, so as to reduce the stress conditions between the chip and the package. Different package materials have different mechanical properties, such as different coefficients of thermal expansion, or xe2x80x9cCTExe2x80x9d. As the die size increases, the CTE between the chip and the package causes increased stress. If this stress increases above the modulus of the materials, there can be fatigue failure at the connection between the chip and the package.
In addition to the CTE differences between the chip and the package materials, there are other mechanical conditions to consider, such as the internal stresses of the package materials that cause bowing of the package. Extreme bowing can prevent the attachment of the die to the substrate, or the substrate to the printed circuit board.
Traditionally, small flip chips (less than 15 mm) have been mounted to single or multi-layer organic substrates, similar to printed circuit boards. Since the CTE of the chip is low (i.e., less than 3 parts per million (PPM)), and the CTE of an organic substrate is high (i.e., in the range of 14 to 17 PPM), a large die (e.g., greater than 26 mm) mounted directly to this type of substrate would be under a very high stress during certain temperature cycles. Ideally, a package must perform over a temperature range of greater than 100 degrees Celsius. For a temperature range of this type, the joint of a soldered connection between the chip and the substrate will fail due to thermal fatigue in less than 500 temperature cycles.
To improve the mechanical performance between a chip and a printed circuit board, glass, ceramic and glass-ceramic mounting layers have been used. These materials, generally referred to as glass-ceramic materials, have coefficients of thermal expansion in the range between 3 and 7 PPM (parts per million) and therefore more closely match the CTE of the semiconductor. This match in CTE lowers the chip-to-substrate stress and allows the chip connection to maintain a bond during temperature cycling. However, this approach results in a secondary problem when the package is mounted to a printed circuit board with a CTE greater than the glass-ceramic CTE. The problem of early temperature cycling failure is now transferred from the die-to-package interface, to the package-to-board interface. Some manufacturers have overcome this secondary problem by employing what is know as xe2x80x9ccolumn grid arrayxe2x80x9d connections, but this technique does not lend itself to more conventional socket and board mounting requirements.
Metal alloys (e.g., a lead tin alloy for example) can be used to form the bumps. Typically, the bumps are dome shaped, and have an average diameter of from 5 mils to 30 mils or greater. Micro ball grid arrays (BGA) are formed in the smaller range, while standard ball grid arrays are formed in the larger size range. The sides of the bumps typically bow or curve outwardly from flat top surfaces. The flat top surfaces of the bumps form the actual regions of contact with the mating contacts on the substrate.
Referring to FIGS. 1-3, a semiconductor die or flip chip 20 is provided with a pattern of solder bumps 22 on an underside or circuit side of the chip. The solder balls 22 align with solder pads 24 on a PC board or similar substrate 26. Flux is normally applied between the solder balls 22 and solder pads 24. Upon heating, the solder pads 24 on the substrate 26 reflow and physically connect with the solder balls 22 on the underside of the chip 20. High lead solder balls 22 typically have a high melting point and therefore do not reflow; eutectic solder balls would melt and slightly collapse and reflow onto the printed circuit board pads. This connection is illustrated in FIG. 2 by deformed solder pad 24xe2x80x2 mating with a solder ball 22. This process eliminates the requirement for wire bonding.
Special liquid epoxy 28 (FIG. 3) is typically used to completely fill the underside of the chip. This is referred to herein as the xe2x80x9cunderfillxe2x80x9d operation. Upon curing, the resulting encapsulation forms a barrier to prevent moisture from contacting and thus corroding the electrical interconnects between the substrate 26 and the chip 20. The epoxy 28 also serves to protect the bonds between the deformed solder pads 24xe2x80x2 and the solder balls 22 by providing thermal stress relief, i.e., accommodating different rates of thermal expansion and contraction. Underfills are often plastic-based materials that flow into small spaces to fill a gap or void 30 between the component (or die) and the substrate to which it is mounted.
Particularly for the large dies over 26 mm, direct access to areas under a chip and removal of residual flux thereunder is restricted. Prior approaches for package construction do not allow effective methods of removing residual flux and other foreign material and objects between the package construction materials that can adversely affect overall packaging performance. Additionally, prior approaches do not allow for an effective method for applying under-fill to uniformly fill between large dies or constructions of a large area package so as to provide more optimal mechanical and thermal performance of the packaging.
In view of the foregoing, it would be highly desirable to provide an improved technique for mounting large semiconductor devices so as to minimize the impact of environmental mismatches in coefficients of thermal expansion. A need exists for a method of construction that allows for a large die to be reliably mounted to a thin package while maintaining the flatness of the substrate, particularly over a large area. In addition, need exists for a process technique for under-filling a flip-chip die to substrates to control the flatness of packages and reduce mechanical and thermal stresses. A need also exists for a method of allowing uniform under-filling of a die-substrate interface. Moreover, a need exists for a method of packaging integrated circuits that can be reliably connected to a motherboard containing other electrical circuits. Further, a need exists for package construction methods that permits effective removal of residual flux and other foreign material and objects between the package construction materials that can adversely affect device performance.
The invention relates to methods of package construction that allow for a first part assembled to a second part having a dissimilar coefficient of expansion. A semiconductor package includes a chip carrier to receive a large semiconductor. The chip carrier has a first coefficient of thermal expansion that is different from the coefficient of thermal expansion of the semiconductor. A stress inhibiting intermediate mounting substrate is connected to the chip carrier through a first array of solder connections. The stress inhibiting intermediate mounting substrate is adapted for connection to a printed circuit board through a second array of solder connections. The stress inhibiting intermediate mounting substrate has a second coefficient of thermal expansion that is larger than the coefficient of thermal expansion of the chip carrier and smaller than the coefficient of thermal expansion of the printed circuit board. The invention disclosed includes a method of mounting together multiple constructions using under-fill material to absorb the stresses in a package construction having materials with different CTE""S, particularly over a large area. In addition, the invention also relates to an effective system and method for removal of residual flux and other foreign material and objects between the package construction materials.